The Intel 8051 microcontroller is one of the earliest popular microcontroller and is still widely used. It is a 40 pin Integrated Circuit which has 128 byte capacity on chip RAM, 4K on chip ROM, two timers, one serial port, four I/O ports and 6 interrupt sources.

In this blog it is shown how intel 8051 chip can be interfaced with external memory. The external memory can be either RAM or ROM of various sizes. Since 8051 has 16 address lines it can be interfaced upto 64K addressable location. If the addressable location is only memory RAM or ROM then the highest capacity memory is 64K RAM or 64K ROM.

One 64K ROM is the 27C64 which is CMOS EPROM. The chip diagram is shown below,

The following schematic shows how a 64K ROM can be interfaced with the 8051 microcontroller.

In the circuit diagram above, since the port 0 pins are address and data multiplexed, they must be demultiplexed using decoder such as 74LS373. The output of the 74LS373 is the address lines A0 to A7. The remaining addresses(A8 to A15) comes from port 2. The address A0 to A7 from the output of 74LS373 are connected to the address lines of A0 to A7 of the 27C64 CMOS EPROM. The address lines A8 to A12 from the microcontroller are connected to the A8 to A12 of the EPROM. The rest of the address lines A13 to A15 are used for chip select. The A13 to A15 address lines are connected to the 74LS138 decoder three inputs. The output is taken from the output line Y7. To enable the decoder the enable G1 must be high and G2Aand G2B must be low. So G1 is connected to the power supply and G2A and G2B are grounded.

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A sequence detector is an example of Finite State Machine because during its operation it undergoes through finite number of states before outputting signal that it has detected a particular sequence.

Consider the figure below which is a sequence detector. The input to this sequence detector is a binary data streams(maybe 01011010101111001010001111) and it has additional two inputs a reset and a clock. The reset when applied puts the sequence detector to a known state. And if the detector detects 111 in sequence then it outputs a 1.

The design of a sequence detector like the one shown above starts with drawing a state diagram from the problem specification. For a sequence detector for example, the question can be specified as design a circuit that detects three consecutive 1s and outputs 1 when the sequence is detected. So in this case the problem can be solved using FSM.

An example of a state diagram is shown below.

Once we have the state diagram, the next step is to draw a state table from the state diagram. The state table contains the same information as the state diagram. The advantage of using now a state table is that it facilitates in deriving next state logic equation and output equation. By contrast a state diagram facilitates in drawing a map of the problem.

A state table for the above state diagram looks like the following:

The next step is to choose the type of flip flop to use for the states. A D flip flop provides the simplest implementation but many times other flip flop such as JK flip flop is more useful as it reduces the combinational circuit implementation as in case of a counter design.

Once you have the state table the next step is to assign state variables to the states. Note that here there are two types of state variables- one for the present state and one for the next state. Following shows the update state table with state assignments-

 Note that the output z column does not have any input x indicated because the design is of Moore type.

After assigning the state variables, the next state variables are solved as a function of the present state variables and the input variables. The tool used to solve the state variables is the commonly used Boolean function solver like the Karnaugh Map.

Finally the circuit is drawn from the knowledge of the next state logic equation and the output equation.

The following shows the simulated waveform obtained.

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