The Intel 8051 microcontroller is one of the earliest popular microcontroller and is still widely used. It is a 40 pin Integrated Circuit which has 128 byte capacity on chip RAM, 4K on chip ROM, two timers, one serial port, four I/O ports and 6 interrupt sources.
In this blog it is shown how intel 8051 chip can be interfaced with external memory. The external memory can be either RAM or ROM of various sizes. Since 8051 has 16 address lines it can be interfaced upto 64K addressable location. If the addressable location is only memory RAM or ROM then the highest capacity memory is 64K RAM or 64K ROM.
One 64K ROM is the 27C64 which is CMOS EPROM. The chip diagram is shown below,
The following schematic shows how a 64K ROM can be interfaced with the 8051 microcontroller.
In the circuit diagram above, since the port 0 pins are address and data multiplexed, they must be demultiplexed using decoder such as 74LS373. The output of the 74LS373 is the address lines A0 to A7. The remaining addresses(A8 to A15) comes from port 2. The address A0 to A7 from the output of 74LS373 are connected to the address lines of A0 to A7 of the 27C64 CMOS EPROM. The address lines A8 to A12 from the microcontroller are connected to the A8 to A12 of the EPROM. The rest of the address lines A13 to A15 are used for chip select. The A13 to A15 address lines are connected to the 74LS138 decoder three inputs. The output is taken from the output line Y7. To enable the decoder the enable G1 must be high and G2Aand G2B must be low. So G1 is connected to the power supply and G2A and G2B are grounded.
In this blog it is shown how intel 8051 chip can be interfaced with external memory. The external memory can be either RAM or ROM of various sizes. Since 8051 has 16 address lines it can be interfaced upto 64K addressable location. If the addressable location is only memory RAM or ROM then the highest capacity memory is 64K RAM or 64K ROM.
One 64K ROM is the 27C64 which is CMOS EPROM. The chip diagram is shown below,
The following schematic shows how a 64K ROM can be interfaced with the 8051 microcontroller.
In the circuit diagram above, since the port 0 pins are address and data multiplexed, they must be demultiplexed using decoder such as 74LS373. The output of the 74LS373 is the address lines A0 to A7. The remaining addresses(A8 to A15) comes from port 2. The address A0 to A7 from the output of 74LS373 are connected to the address lines of A0 to A7 of the 27C64 CMOS EPROM. The address lines A8 to A12 from the microcontroller are connected to the A8 to A12 of the EPROM. The rest of the address lines A13 to A15 are used for chip select. The A13 to A15 address lines are connected to the 74LS138 decoder three inputs. The output is taken from the output line Y7. To enable the decoder the enable G1 must be high and G2Aand G2B must be low. So G1 is connected to the power supply and G2A and G2B are grounded.
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